The present invention relates to a semiconductor memory device, and particularly a DRAM (dynamic random access memory) formed of an IC chip which is capable of selective connection, in the process of production, for operation in a page mode or for operation in a nibble mode.
In recent years, two types of DRAMs, namely those operable in the page mode and those operable in the nibble mode are widely used. To avoid the necessity to prepare two different types of IC chips for the respective modes, thereby to improve design efficiency and production efficiency, the memory manufacturers make arrangement to prepare memories (half-finished) of identical configuration (IC chips) and to prepare two different masks for forming aluminum interconnection, or to form additional bonding pads, so that by selective use of the masks for forming interconnection or the bonding pads, the memories (final products) which operate in the desired mode can be ultimately obtained.
As an example, an arrangement where masks for forming aluminum interconnection are used for the selective production will be described.
FIG. 1 is a block diagram showing a DRAM on which the aluminum interconnection is selectively formed for the selective production. As illustrated, it comprises memory cell arrays CR comprising memory cells arranged in rows and columns to form matrixes, and row decoders RD and column decoders CD. It also comprises array control circuit AC which comprises a CASN buffer, or a first CAS buffer 1, and a CAS buffer or a second CAS buffer 2.
A feature of this DRAM is the provision of the two buffers 1, 2. The output signal of the CASN buffer 1 is used to control a write buffer 3, a data input buffer 4, a four-bit shift register 5, an output buffer 6 and a 1-of-4 data I/O gating circuit 7. The output signal of the CAS buffer 2 is used to control an address buffer 8, column decoders 9 and pre-amplifiers 10.
The CAS buffer circuit 2 includes a mode selection circuit 11, shown to be a switch which connects a node 11C to either a node 11A or a node 11B. The node 11A is connected to the output .phi.D of a circuit comprising transistors 12, 13. The node 11B is connected to a voltage source Vcc. For production of a memory operable in the page mode, aluminum interconnection is formed to connect the node 11C to the node 11B. For production of a memory operable in the nibble mode, aluminum interconnection is formed to connect the node 11C to the node 11A. For this purpose, two types of masks for forming aluminum interconnection are prepared, and one of them is used depending on which type of the memory is desired.
The operation of the DRAM will now be described.
FIG. 2 shows a RAS signal, a CASN signal, a .phi.D signal and CAS signal generated in the chip where the node 11C is connected to the node 11A, i e., where the memory is operable in the nibble mode. As will be seen from FIG. 2, the CASN signal is an inversion of an external CAS signal and in synchronism with the external CAS signal. The .phi.D signal falls to the "L" level when the CASN signal rises to "H" (so that the transistor 13 conducts while the transistor 12 is nonconductive), and is held at "L" until the RAS signal rises to "H". The CAS signal outputted from the CAS buffer 2 having a NAND gate formed of transistors 14, 15 rises to "H" as the external CAS signal falls to "L", and is held at "H"even if the external CAS signal thereafter rises to "H". The CAS signal falls to "L" when the .phi.D signal rises to "H", i.e., the external RAS signal rises to "H".
With such an arrangement, the write buffer 3, the data input buffer 4, the four-bit shift register 5, the output buffer 6, and the I/O gating circuit 7 are fed with the CASN signal in synchronism with the external CAS signal, so that they are operated in synchronism with the external CAS signal.
The address buffer 8, the column decoders 9 and the preamplifiers 10, which are controlled by the CAS signal, begin operation upon the CAS signal rising to "H" and continue to be in the operating state until the external RAS signal rises to "H". The operation in the nibble mode is thereby achieved.
For production of a memory operable in the page mode, the node 11C is connected to the node 11B, i.e., to the power source Vcc. The transistor 14 is therefore kept conductive. The CAS buffer 2 is equivalently identical to the CASN buffer 1, so that the CAS signal is in synchronism with the external CAS signal. The address buffer 8, the column decoders 9 and the preamplifiers 10 repeat being set and reset. The operation in the page mode is thereby achieved.
A disadvantage of the above-described prior art memory device is the necessity to prepare two different types of masks for forming aluminum interconnection. Moreover, it is necessary to manage manufacture as to which of the masks should be used for the particular production. Furthermore, since the selective formation of the interconnection is conducted during the wafer process, it is difficult to meet an urgent demand, e.g., an order with a short delivery time.
In the other of the above-mentioned prior art, where special pads are formed, the selective formation can be conducted during the assembly, so that it is easier to meet an urgent demand. But, this arrangement is disadvantageous in that the pads require a relatively large area, so that the loss is considerable particularly with mass-produced DRAMs.